ECE 4040/5040: Introduction to Hardware Security
Department of Electrical and Computer Engineering, University of Idaho
Semester: Fall 2026
Instructor: Prof. Zain Ul Abideen (zabideen@uidaho.edu)
Course materials: The official schedule, assignments, grades, and protected materials are provided through Canvas.
This course introduces the security principles, attack models, and design methods needed to build and evaluate trustworthy hardware. It connects threats across the integrated-circuit lifecycle with practical analysis of digital designs, hardware security primitives, and countermeasures.
Learning Objectives
By the end of the course, students will be able to:
- Explain hardware-security threats across design, fabrication, test, deployment, and the global IC supply chain.
- Construct threat models for adversaries at the software, firmware, board, and silicon levels.
- Analyze hardware Trojans, reverse-engineering risks, IP piracy, counterfeiting, and invasive and non-invasive attacks.
- Evaluate logic locking, circuit obfuscation, split manufacturing, and related design-for-trust countermeasures.
- Characterize physical unclonable functions and true random-number generators using security and reliability metrics.
- Explain power, electromagnetic, timing, and fault-injection attacks and select appropriate countermeasures.
- Apply secure-design and verification practices to RTL and hardware implementations.
Major Topics
- Foundations of hardware trust and assurance
- IC supply-chain threats and counterfeit detection
- Hardware Trojans and malicious modifications
- Reverse engineering, IP protection, logic locking, and obfuscation
- PUFs, TRNGs, entropy, reliability, and helper-data methods
- Side-channel analysis and leakage assessment
- Voltage, clock, electromagnetic, and laser fault injection
- Secure EDA, formal verification, and security-aware implementation
- Security of cryptographic and post-quantum hardware
Prerequisites
Digital logic and computer organization, or instructor permission. Experience with Verilog or SystemVerilog is helpful for laboratory and project work.
ECE 5040 Graduate Expectations
Graduate students complete an additional research-oriented component that includes a deeper literature review, an advanced implementation or evaluation, and a written technical report supported by measured results.
Professional and Academic Expectations
- Document assumptions, threat models, experimental setup, and limitations clearly.
- Use only authorized hardware, datasets, and systems for security experiments.
- Follow University of Idaho academic-integrity requirements and the course policy posted in Canvas.
- Disclose and cite any permitted use of AI-assisted tools according to assignment instructions.